Domino logic is a precharged, non-inverting family of CMOS logic that uses multiple clock phases to achieve high-speed operation. Domino logic is faster than standard static logic, but it is more difficult to use because of its increased complexity, primarily in the clocking network. Using dynamic logic, such as domino logic, is a well-known way of gaining speed in high performance designs. However, dynamic logic tends to use more integrated circuit die area and consumes more power as compared to static logic.
Typically domino logic operates in two phases: precharge and evaluate. During the precharge phase, when the clock is low, the output of the cell goes low. During the evaluate phase, when the clock is high, the output of the cell can only transition from a low to a high value. This is in contrast to standard static logic typically used with CMOS technology. In static logic designs, the output of the cell can rise or fall, depending on the input conditions, during normal operation.
The clocking scheme consists of three or more skewed clock phases operating at the same frequency. Typically, the clock phases have a balanced duty cycle and are equally skewed in order to maximize their overlap, since the tolerance to the clock uncertainty increases with the phase overlap.
What is desired is a method for replacing domino logic cells with smaller, less complicated, and lower-power static cells in selected parts of a logic circuit design that are not impacted by the lower operating speeds of the static cells.